I’m a 6th year Ph.D candidate at Boston University (graduating Spring/Summer 2016!). I work with Ajay Joshi and the ICSG research group where I design hardware and software for neural networks. While I specialize in digital design, I’ve found the most enjoyable projects are team-based and span the entire hardware/OS/software stack like some of our current work funded by the NSF.
This webpage serves as a CV, but a downloadable PDF is provided here.
I currently collaborate with:
- Jonathan Appavoo
- Margo Seltzer
- Steve Homer
- Amos Waterland
- Tommy Unger
- Marcia Sahaya-Louis
- Leila Delshad
- Ph.D Computer Engineering, Boston University 2016 (expected August)
- BS Electrical Engineering, Boston University 2010
I explore hardware-based biologically-inspired approaches to computing. My work-in-progress thesis, Viable Neuromorphic Computing via Neural Network Accelerators, focuses on the design of neural network accelerator hardware that treats neural network computation as a first-class functional primitive. This includes fixed-topology neural network accelerators as well as dynamically managed, variable-topology ones that can be shared between multiple processes. These dynamic, shared accelerators require supporting hardware and user/supervisor software for safe use. This work is in the process of being open sourced. Specific achievements include: * Implementation of a fixed-topology neural network accelerator in Verilog * Implementation of an arbitrary-topology accelerator (modeled in C++ and interfaced with gem5) in SystemVerilog and Chisel * Design of user and supervisor software libraries in embedded assembly and C that enables safe management of neural network computation * Integration of supervisor software with the Linux kernel * Evaluation as a rocket-chip custom coprocessor on FPGA * The development of the arbitrary-topology variant, X-FILES/DANA, is available on GitHub
Prior research involved investigating biologically-inspired methods to computing optical flow. One of these approaches, using variable sized Gabor filters, I implemented in Verilog and tested on a Xilinx Virtex-6 FPGA with a manually interfaced CMOS camera. This involved the design of various pipelined computer arithmetic blocks (a CORDIC unit, a divider, a square root unit, and a linear interpolation unit). This system was controlled over a UART interface by Matlab. These units are available in my public Verilog repo.
This work was funded by a NASA Space Technology Research Fellowship from 2012–2016, through BU’s Center for Computational Neuroscience and Neural Technology (CompNet) in 2011, with a Dean’s Fellowship in 2010, and for my collaborators through the NSF.
- S. Eldridge, A. Waterland, M. Seltzer, J. Appavoo, and A. Joshi, Towards General-Purpose Neural Network Computing, Parallel Architectures and Compilation Techniques (PACT) 2015. [ paper ] [ presentation ]
- S. Eldridge, F. Raudies, D. Zou, and A. Joshi, Neural Network-Based Accelerators for Transcendental Function Approximation, Great Lakes Symposium on VLSI (GLSVLSI) 2014. [ paper ] [ presentation ]
- F. Raudies, S. Eldridge, A. Joshi, and M. Versace, Learning to Navigate in a Virtual World Using Optic Flow and Stereo Disparity Signals, Artificial Life and Robotics, 19:2 (2014). [ paper ]
Workshop Presentations and Posters
- S. Eldridge, Dong, H., Unger, T., Sahaya Louis, M., Delshad Tehrani, L., Appavoo, J., and Joshi, A. X-FILES/DANA: RISC-V Hardware/Software for Neural Networks, Fourth RISC-V Workshop 2016. [ poster ]
- S. Eldridge, Sahaya Louis, M., Unger, T., Appavoo, J., and Joshi, A. Learning-on-chip using Fixed Point Arithmetic for Neural Network Accelerators, Design Automation Conference (DAC) 2016. [ poster ]
- S. Eldridge., T. Unger, M. Sahaya Louis, A. Waterland, M. Seltzer, J. Appavoo, and A. Joshi, Neural Networks as Function Primitives: Software/Hardware Support with X-FILES/DANA, Boston Area Architecture Workshop (BARC) 2016. [ paper ] [ presentation ] [ poster ]
- S. Eldridge and A. Joshi, Exploiting Hidden Layer Modular Redundancy for Fault-Tolerance in Neural Network Accelerators, Boston Area Architecture Workshop (BARC) 2015. [ paper ] [ presentation ]
- J. Appavoo, A. Waterland, K. Zhao, S. Eldridge, A. Joshi, and M. Seltzer, Programmable Smart Machines: A Hybrid Neuromorphic Approach to General Purpose Computation, Workshop on Neuromorphic Architectures (NeuroArch) at 41st International Symposium on Computer Architecture (ISCA) 2014. [ paper ]
- S. Eldridge, F. Raudies, and A. Joshi, Approximate Computation using Neuralized FPU, Brain-Inspired Computing (BIC) Workshop at 40th International Symposium on Computer Architecture (ISCA) 2013. [ paper ]
Patents and Patent Applications
- V. Gopal, J. D. Guilford, S. Eldridge, G. M. Wolrich, E. Ozturk, W. K. Feghali, Digest generation, US Patent Application 13/995,236, 2011. [ patent application ]
- Common Verilog – Contains basic Verilog modules with a high probability of reuse [ GitHub ]
- LaTeX Build Flow – Makefile-driven latexmk LaTeX paper/presentation build flow that cleans up source files to one-sentence-per-line format, converts SVG graphics to EPS, and supports the use of Colorbrewer colors [ GitHub ]
- Make Markdown – Makefile-driven build system for converting GitHub-flavored markdown to HTML and a simple way of keeping daily notes (a Captain’s Log). This is used in a slightly modified way to create this website. [ GitHub ]
- Ulysses – A Perl script for parsing plain text results from intercollegiate figure skating competitions and computing the totals and statistics for each college. [ GitHub ]
- Senior Design Project – Worked on a five person team to build a PCB that interfaced with an Altium FPGA development board. We demonstrated the utility of this board with a real time, color-threshold pan/tilt camera-based object tracking application. My responsibilities included implementation of the complete system on FPGA and a PID control system for a soft-core microprocessor. Unfortunately, no videos exist of the final, working system… [ BU ECE Press ]
- FPGA Frogger – Final project for Advanced Digital Design in Verilog (Fall 2009) that re-implements a Frogger-style game on a Spartan 3 Xilinx FPGA. This included a custom PS/2 keyboard interface in Verilog, sprite storage using block RAMs, and pixel generation using entirely combinational logic (an interesting design choice). [ video ]
- Proportionally Controlled Flashlight Follower – Final project for Microprocessors (Spring 2009) that uses an MSP430 and a breadboard-designed H-bridge to control a motor pulled from a CD drive and, using the difference in intensity from two photodiodes, track a flashlight. [ video ]
- NASA Jet Propulsion Lab, Pasadena, CA (Summer 2013–2015) – As part of a NASA Space Technology Research Fellowship, I’ve spent the past three summers at JPL continuing my research into biologically-inspired hardware accelerators for computing applications.
- Intel Corporation, Hudson, MA (Summer 2011) – I worked as a graduate technical intern on a testing and validation team responsible for writing tests and modifying SystemVerilog HDL sources for the memory controller of an Intel server microprocessor.
- Intel Corporation, Hudson, MA (Summer 2010) – As a graduate technical intern with a software research group, I wrote hashing functions in x86 assembly and evaluated them in terms of performance and uniformity.
I’m comfortable at all levels of hardware and software development. Many years of this has left me with an “anything is likely possible” attitude as it relates to engineering. I greatly enjoy working with diverse teams on projects that span the complete hardware/software stack.
I’m well versed in Verilog and SystemVerilog as well as a new HDL called Chisel that brings the functional and object oriented power of Scala to hardware design.
I’m comfortable in C/C++, Perl, Python, Scala, Matlab, Assembly (x86 and RISC-V specifically), Bash scripting (including writing Makefiles for everything) and LaTeX. I also have experience writing Java and TCL.
I prefer a command-line driven development environment in GNU/Linux with text editing in Emacs (though I know enough vi to get by), but am also comfortable in Windows or OS X. I’ve hacked up gem5 and have used McPAT and Cacti for architectural simulations. I enjoy open source development and will opt to do hardware development with Icarus Verilog and GTKWave (and I have a script that helps populate and group signals by module for GTKWave). At BU, we use a Cadence (RC compiler/SoC Encounter) toolflow for evaluating hardware designs. I’ve made contributions to this workflow that interfaces this with a Chisel front-end for Verilog generation, post place-and-route VCD generation with Modelsim, and VCD-based power estimation with SoC Encounter. I’ve used Xilinx ISE and Vivado for FPGA development and have had success scripting out the entire Verilog to Bitstream generation in TCL.
- NASA Space Technology Research Fellowship – Four year NASA fellowship from 2012–2016 for work titled Biologically-inspired Hardware for Land/Aerial Robots where I’ve designed neural network accelerators and evaluated their energy efficiency and capacity for fault-tolerance
- CELEST/CompNet Award – Awarded at Boston University’s 2012 Science Day for work involving the FPGA implementation of a biologically-inspired optical flow algorithm
- Dean’s Fellowship – One year fellowship during my first year as a Ph.D student at BU in 2010
- P. T. Hsu Memorial Award for Outstanding Senior Design Project – Awarded to the top senior design team from the 2010 ECE graduating class
I’ve been figure skating since I was 5, got to Nationals one year, and have skated on the BU collegiate team for a long time. Some videos are below:
- University of Delaware Intercollegiate Competition 2014 – Short program at the University of Delaware [ video ]
- Celebration of BU Show 2012 – Skating with the Boston Pops [ video ] [ video ]
- Intercollegiate Team Nationals 2011 – Skating in Ann Arbor, MI [ video ]
- Eastern Sectionals October 2008 – Skating at the Skating Club of Boston [ video ]